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high speed , dual , 4 a mosfet driver with thermal protection ADP3624/adp3634 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461. 3113 ? 2009 analog devices, inc. all rights reserved. features industry - standard - compatible p inout high c urrent d rive c apability precise t hreshold shutdown c omparator uvlo with hysteresis over t emperature w arning s ignal over t emperature s hutdown 3.3 v-c ompatible i nputs 10 ns t yp ical r ise t ime and f all t ime @ 2. 2 nf load matched p ropagation d elays between c hannels fast p ropagation d elay 9.5 v to 18 v s upply v oltage (adp3634 ) 4.5 v to 18 v s upply v oltage (ADP3624 ) parallelable d ual o utputs rated from ? 40 c to 85 c a mbient t emperature thermally en hanced p ackages , 8- lead soic _n_ep and 8- lead mini_so_ep applications ac - to - dc s witch m ode p ower s upplies dc - to - dc p ower s upplies synchronous r ectification motor d rives g eneral d escription the adp36 24/ adp36 34 are high current drive, dual high speed drivers, capable of driving two independent n - channel power mosfets. the part use s the industry - standard footprint but add s high speed switching performance and improved system reliability. the part has an internal t emperature sensor a nd provides two levels of over temperature protection , an overtemperature warning and an overtemperature shutdown at extreme junction temperatures. the sd function , generated from a precise internal comparator , provides fast system enabl e or shutdown . this feature allows redundant over voltage protection, complementing the protection inside the main controller device, or provide s safe system s hutdown in the event of an over temperature warning. wide input voltage range allows the driver to be compatible with both analog and digital pwm controllers. digital p ower controllers are supplied from a low voltage supply, and the driver is supplied from a higher voltage supply. the adp36 24/adp3634 add uvlo and hysteresis functions , allowing safe sta rtup and shutdown of the higher voltage supply when used with low voltage digital controllers. the device family is available in thermally enhanced soic _ n_ ep and m ini_so_ep packaging to maximize high frequency and current switching in a small printed circ uit board ( pcb ) area. functional b lock d iagram 1 8 2 7 3 6 4 5 overtempera ture protection ADP3624/adp3634 noninverting in a pgnd inb sd ou ta vdd outb otw v dd v dd inverting noninverting inverting uvlo v en 08132-101 figure 1.
ADP3624/adp3634 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 4 absolute maximum ra tings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 te st c irc uit ........................................................................................ 9 theory of operation ...................................................................... 10 input drive requirements (ina, inb, sd) ............................ 10 low - side drivers (outa, outb) .......................................... 10 shutdown (sd) function .......................................................... 10 overtemperature protections ................................................... 10 supply capacitor selection ....................................................... 11 pcb layout co nsiderations ...................................................... 11 parallel operation ...................................................................... 11 thermal considerations ............................................................ 12 outline dimensions ....................................................................... 13 ordering guide .......................................................................... 13 revision history 5 /09 revision 0: initial version
ADP3624/adp3634 rev. 0 | page 3 of 16 specifications v dd = 1 2 v, t j = ?4 0c to + 125 c, unless otherwise noted. 1 table 1 . parameter symbol test conditions /comments min typ max unit supply supply voltage range v dd adp363 4 9.5 18 v v dd adp362 4 4.5 18 v supply current i dd no s witching , ina a nd inb disabled 1. 2 3 ma standby current i sby sd = 5 v 1. 2 3 ma uvlo turn - on threshold voltage v uvlo_ on v dd rising , t a = 25c , adp3634 8.0 8.7 9.5 v v uvlo_on v dd rising, t a = 25c , ADP3624 3.8 4.2 4.5 v turn - off threshold voltage v uvlo_off v dd falling, t a = 25c , adp3634 7.0 7.7 8.5 v v uvlo_off v dd falling, t a = 25c , ADP3624 3.5 3.9 4.3 v hysteresis adp3634 1.0 v ADP3624 0.3 v digital inputs (ina, inb, sd) input voltage high v ih 2.0 v input voltage low v il 0.8 v in put current i in 0 v < v in < v dd ? 20 +20 a sd threshold high v sd _h 1.19 1.28 1.38 v v sd _h t a = 25c 1.21 1.28 1.3 5 v sd threshold low v sd _l t a = 25c 0.9 5 1.0 1.05 v sd hysteresis v sd _ hyst t a = 25c 24 0 28 0 320 mv internal pu ll- up / pull - down current 6 a outputs (outa, outb) output resistance, unbiased vdd = p gnd 80 k? peak source current see figure 17 4 a peak sink current see figure 17 ?4 a switching time outa, outb rise time t rise c load = 2.2 nf, s ee figure 3 10 25 ns outa, outb fall time t fal l c load = 2.2 nf , s ee figure 3 10 25 ns outa, outb rising propagation delay t d1 c load = 2.2 nf , s ee figure 3 14 30 ns outa, outb falling propagation delay t d2 c load = 2.2 nf, s ee figure 3 22 35 ns sd propagation delay low t d l_ sd see figure 2 32 45 ns sd propagation delay high t dh_ sd see figure 2 48 75 ns delay matching between channels 2 ns over temperature protection over t emperature warning threshold t w see figure 5 120 135 150 c overt emperature shut down threshold t sd see figure 5 150 165 180 c temperature hysteresis for s hutdown t hys _sd see figure 5 30 c temperature hysteresis for w arning t hys_w see figure 5 10 c overt emperature warning lo w v otw_ol open d rain , ? 500 a 0.4 v 1 all lim its at temperature extremes guaranteed via correlation using standard statistical quality control (sqc) methods.
ADP3624/adp3634 rev. 0 | page 4 of 16 timing characteristics sd outa, outb 90% t dl_sd 10% t dh_sd 08132-002 figure 2. shutdown timing diagram ina, inb outa, outb t d1 t rise 10% 90% 10% 90% v inh v inl t d2 t fall 08132-003 figure 3. output timing diagram normal operation uvlo mode outputs disabled v dd v uvlo_on v uvlo_off uvlo mode outputs disabled 0 8132-005 figure 4. uvlo function ot shutdown outputs disabled normal operation normal operation t j t w t sd t sd ? t hyst_sd t w ? t hyst_w ot warning outputs enabled ot warning outputs enabled otw 0 8132-006 figure 5. overtemperature warning and shutdown
ADP3624/adp3634 rev. 0 | page 5 of 16 absolute maximum rat ings table 2. parameter rating vdd ?0.3 v to +20 v outa, outb dc ?0.3 v to v dd + 0.3 v <200 ns ?2 v to v dd + 0.3 v ina, inb, sd ?0.3 v to v dd + 0.3 v esd human body model (hbm) 3 .5 kv field induced charged device model (ficdm) , soic_n_ep 1.5 kv field induced charged device model (ficdm), mini_so_ep 1.0 kv j a , soic_n _ep 1 jedec 4- layer board 59 c/w ja , m ini_so _ ep 1 jedec 4- layer board 43 c/w junction temperature range ?4 0c to + 150c storage temperature range ? 65c to +150c lead temperature soldering (10 sec) 300c vapor phase (60 sec) 215c infrared (15 sec) 260c 1 ja is measured per jedec standard s jesd51 - 2, jesd51 - 5, and j esd51 - 7 as appropriate with the exposed pad soldered to the pcb. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other co nditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ADP3624/adp3634 rev. 0 | page 6 of 1 6 pin configuration and function descri ptions sd 1 in a 2 pgnd 3 inb 4 otw 8 ou ta 7 vdd 6 outb 5 ADP3624/ adp3634 top view (not to scale) notes 1. the exposed p ad of the p ackage is not direct ly connected to an y pin of the p ackage, but it is electrical ly and thermal ly connected t o the die substr a te, which is the ground of the device. 08132-001 figure 6 . pin configuration table 3 . pin function descriptions pin o. neonic description 1 sd output shutdown . when high , this pin disables normal operation, forcing outa and outb low. 2 ina input pin for channel a gate driver . 3 p gnd ground. this pin should be closely connected to the source of the power mosfet. 4 inb input pin for channel b gate driver . 5 outb output pin for channel b gate driver . 6 vdd power supply voltage . this pin s hould be bypassed to p gnd with a ~1 f to 5 f ceramic capacitor. 7 outa output pin for channel a gate driver . 8 otw over t emperature warning flag , open drain , active low .
ADP3624/adp3634 rev. 0 | page 7 of 16 typical performance characteristics 3 4 5 6 7 8 9 ?50 ?30 ?10 10 30 50 70 90 110 130 temperature (c) uvlo (v) v uvlo_on v uvlo_off v uvlo_on v uvlo_off adp3634 ADP3624 08132-022 figure 7. uvlo vs. temperature 0 2 4 6 8 10 12 14 ?50 ?30 ?10 10 30 50 70 90 110 130 temperature (c) t fall t rise time (ns) 08132-010 figure 8. rise and fall times vs. temperature 0 10 20 30 40 50 60 ?50 ?30 ?10 10 30 50 70 90 110 130 temperature (c) time (ns) v dd = 12v t dh_sd t dl_sd t d2 t d1 08132-011 figure 9 . propagation delay vs. temperature 0 5 10 15 20 25 0 5 10 15 20 v dd (v) time (ns) t fall t rise 08132-012 figure 10 . rise and fall times vs. v dd 0 10 20 30 40 50 60 70 0 5 10 15 20 t dl_sd t d2 t d1 t dh_sd v dd (v) time (ns) 08132-013 figure 11 . propagation delay vs. v dd 0 200 400 600 800 1000 1200 1400 ?50 ?30 ?10 10 30 50 70 90 110 130 temperature (c) shutdown threshold (mv) sd threshold hysteresis sd threshold high sd threshold low 08132-014 figure 12 . shutdown threshold vs. temperature
ADP3624/adp3634 rev. 0 | page 8 of 16 08132-023 1 2 outa/outb ina/inb v dd = 12v time = 20ns/div figure 13 . typical rise propagation delay 08132-024 1 2 v dd = 12v time = 20ns/div outa/outb ina/inb figure 14 . typical fall propagation delay 08132-025 1 2 v dd = 12v time = 20ns/div outa/outb ina/inb figure 15 . typical rise time 08132-026 1 2 v dd = 12v time = 20ns/div outa/outb ina/inb figure 16 . ty pical fall time
ADP3624/adp3634 rev. 0 | page 9 of 16 test circuit ina vdd v dd pgnd ADP3624/adp3634 outa outb inb sd otw 1 3 8 7 6 5 a b 2 4 c load 100nf ceramic 4.7f ceramic scope probe 08132-007 figure 17 . test circuit
ADP3624/adp3634 rev. 0 | page 10 of 16 theory of operation the ADP3624/adp3634 dua l drivers are optimized for driving two independent enhancement n - channel mosfets or insulated gate bipolar transistors ( ig bts ) in high switching frequency applications . these applications require high speed, fast rise and fall times , as well as short propagation delays. the capacitive nat ure of the aforementioned gated devices requires high peak current capability as well. ina vdd v dd pgnd ADP3624/adp3634 outa outb inb sd otw 1 3 8 7 6 5 a b 2 4 v ds v ds 08132-017 figure 18 . typical application circuit input d rive r equirements (ina, inb, sd ) the ADP3624/adp3634 inputs ar e designed to meet the requirements of modern digital power controllers: the signals are compatible with 3.3 v logic levels. at the same time, the input structure allows for input voltages as high as v dd . the signals applied to the inputs ( ina and i nb) sho uld have steep and clean fronts. it i s not recommended to apply slow changing signals to drive these inputs because they can result in multiple switching when the thresholds are crossed, cau sing damage to the power mosfet or i g bt. an internal pull - down res istor is present at the input, which guaran tee s that the power device is off in the event that the input is left floating. the sd input has a precision comparator with hysteresis and is therefore suitable for slow changing signals (such as a scaled down ou tput voltage ); see the shutdown (sd) function section for more details on this comparator. low- side driver s (outa, outb) the ADP3624/adp3634 dual drivers are designed to drive ground - referenced n - channel mosfet s . the bias is inter nally connected to the v dd supply and pgnd. when the ADP3624/adp3634 are disabled, both low - side gates are held low. an internal impedance is present between the outa/outb pin s and gnd , even when v dd is not present ; this feature ensures that the power mosf et is normally off when bias voltage is not present. when interfacing the ADP3624/adp3634 to external mosfets, the designer should consider ways to make a robust design that minimizes stresses on both the driver and the mosfets. these stresses include exce eding the short time duration voltage ratings on the out a and outb pins , as well as the external mosfet. power mosfets are usually selected to have a low on resistance to minimize conduction losses, which usually implies a large input gate capacitance and gate charge. shutdown ( sd ) function the ADP3624/adp3634 feature an advanced shutdown function, with accurate threshold and hysteresis. the sd signal is an active high signal . an internal pull - up is present on this pin and , therefore , it is necessary to pu ll down the pin externally in order for drivers to operate normally. in some power systems , it is sometimes necessary to provide an additional over voltage protection ( ovp ) or overcurrent protection ( ocp ) shutdown signal to turn off the power devices (mosfe ts or igbts) in case of failure of the main controller. an accurate internal reference is used for the sd comparator so that it can be used to detect ovp or ocp fault conditions. ac input dc output + ? ou ta pgnd v en sd ADP3624/adp3634 08132-018 figure 19 . shutdown function used for redundant ov p over t emperature protectio ns the ADP3624/adp3634 provide two levels of over temperature protections: ? over t emperature w arning (otw) ? over t emperature shut down the o ver t emperature w arning (otw) is an open - drain logic signal and is active low. in normal operati on, when no thermal warning is present, the signal is high, whereas when the warning threshold is crossed, the signal is pulled low.
ADP3624/adp3634 rev. 0 | page 11 of 16 ADP3624/ adp3634 adp1043 a 3.3v vdd pgnd pgnd flagin vdd otw ADP3624/ adp3634 otw 08132-019 figure 20 . otw signaling scheme example the otw open - drain configuration allows connect ion of mu ltiple devices to the same warning bus in a wir e- or e d configuration , as shown in figure 20. the o ver t emperature shut down turn s off the device to protect it in the event that the die temperature exceed s the abs olute maximum limit in table 2 . supply capacitor sel ection for the supply input (v dd ) of the ADP3624/adp3634 , a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents that are drawn. an improper decoupling c an dramatically increase the rise times, cause excessive resonance on the out a and outb pin s, and , in some extreme cases , even damage the device, due to inductive overvoltage on the vdd or out a/outb pins. the minimum capacitance required is determined by t he size of the gate capacitances being driven, but as a general rule , a 4.7 f, low esr capacitor should be used . multilayer ceramic chip (mlcc) capacitors provide the best combination of low esr and small size. use a smaller ceramic capacitor (100 nf) wi th a better high frequency characteristic in parallel to the main capacitor to further reduce noise. keep the ceramic capacitor as close as possible to the ADP3624/ adp3634 , and minimize the length of the traces going from the capacitor to the power pins o f the device. pc b layout consideration s use the following general guidelines when designing printed circuit boards (pcbs) : ? trace out the high curren t paths and use short, wide (>4 0 mil) traces to make these connections. ? minimize trace inductance between t he outa and outb outputs and mosfet gates. ? connect the pgnd pin of the ADP3624/adp3634 as closely as possible to the source of the mosfets. ? place the v dd bypass capacitor as close as possible to the v dd and pgnd pins. ? use vias to other layers, when possibl e, to maximize thermal conduction away from the ic. figure 21 sh ows an example of the typical layout based on the preceding guidelines. 08132-027 figure 21 . exte rnal component placement example note that the expo sed pad of the package is not directly connected to any pin of the package, but it is electrically and thermally connected to the die substrate, which is the ground of the device. p arallel o peration the two driver channels present in the ADP3624/adp3634 ca n be combined to operate in parallel to increase drive capability and minimize power dissipation in the driver. in this configuration , ina and inb are connected together , and out a and outb are connected together . the connection scheme is shown in figure 22. particular attention must be paid to the layout in this case to optimize load sharing between the two drivers. ina vdd v dd pgnd ADP3624/adp3634 outa outb inb sd otw 1 3 8 7 6 5 a b 2 4 v ds 08132-021 figure 22 . parallel operation
ADP3624/adp3634 rev. 0 | page 12 of 16 t hermal considerations when designing a power mosfet gate dr ive , the maximum power dissipation in the driver must be considered to avoid exceeding maximum junction temperature. data on package thermal resistance is provided in table 2 to help the designer in this task. there are several eq ually important aspects that must be considered. ? gate charge of the power mosfet being driven ? bias voltage value used to power the driver ? maximum switching frequency of operation ? value of external gate resistance ? maximum ambient (and pcb) temperature ? type of package all of these factors influence and limit the maximum allowable power dissipated in the driver. the gate of a power mos fet has a non linear capacitance characteristic . for this reason , although the input capacitance is usually reported in the mos fet data sheet as c iss , it is not useful to calculate power losses. the total gate charge necessary to turn on a power mosfet device is usually reported on the device data sheet under q g . this parameter varies from a few nanocoulombs ( nc ) to several hundre ds of nc , and is specified at a specific v gs value (10 v or 4.5 v). the power necessary to charge and then discharge the gate of a power mosfet can be calculated as: p gate = v gs q g f sw w here: v gs is the bias voltage powering the driver (vdd) . q g is th e total gate charge . f sw is the max imum switching frequency . th e power dissipated for each gate (p gate ) still needs to be multiplied by the number of drivers (in this case , 1 o r 2) being used in each package , and it represents the total power dissipated in charging and discharging the gates of the power mosfet s. not all of this power is dissipated in the gate driver because part of it is actually dissipate d in the external gate resistor , r g . the larger the external gate resistor , the smaller the amount of p ower that is dissipated in the gate driver. in modern switching power applications , the value of the gate resistor is kept at a minimum to increase switching speed and minimize switching losses. in all practical applications where the external resistor is in the order of a few ohms, the contribution of the external resistor can be neglected , and the extra loss is assumed in the driver, providing a good guard band to the power loss calculations. in addition to the gate charge losses , there are also dc bias l osses, due to the bias current of the driver. this current is present regardless of the switching. p dc = v dd i dd the total estimated loss is the sum of p dc and p gate . p loss = p dc + ( n p gate ) w here n is the number of gates driven. when the total power l oss is calculated , the temperature increase can be calculated as t j = p loss ja design example for example , consider driving two irfs4310z mosfets with a v dd of 12 v at a switching frequency of 300 khz , using an ADP3624 in the soic package. the m ax imum pcb temperature considered for this design is 85 c. from the mos fet data sheet , the total gate charge is q g = 120 nc . p gate = 12 v 120 nc 300 khz = 432 mw p dc = 12 v 1.2 ma = 14.4 mw p loss = 14.4 mw + (2 432 mw) = 878.4 mw from the mosfet data sheet , the soic _n_ ep thermal resistance is 59 c / w. t j = 878.4 mw 59c/w = 52.7c t j = t a + t j = 137.7c t j max this estimated junction temperature does not factor in the power dissipated in the external gate resistor and , therefore , provides a certain guard band. if a lower junction temperature is required by the d esign, the m ini_so_ ep package can be used, which provides a thermal resistance of 43 c/w, so that the maximum junction temperature is : t j = 878.4 mw 43c/w = 37 .7c t j = t a + t j = 122 .7c t j max other option s to reduce power dissipation in the drive r include reducing the value of the v dd bias voltage, reducing switching fre - quency , and choosing a power mosfet wi t h smaller gate charge.
ADP3624/adp3634 rev. 0 | page 13 of 16 outline dimensions compliant t o jedec s t andards ms-012-a a controlling dimensions are in millimeter; inch dimensions (in parentheses) are rounded-off millimeter equi v alents for reference on ly and are not appropri a te for use in design. 072808- a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.050) 0.40 (0.016) 0.50 (0.020) 0.25 (0.010) 45 8 0 1.75 (0.069) 1.35 (0.053) 1.65 (0.065) 1.25 (0.049) sea ting plane 8 5 4 1 5.00 (0.197) 4.90 (0.193) 4.80 (0.189) 4.00 (0.157) 3.90 (0.154) 3.80 (0.150) 1.27 (0.05) bsc 6.20 (0.244) 6.00 (0.236) 5.80 (0.228) 0.51 (0.020) 0.31 (0.012) coplanarit y 0.10 top view 2.29 (0.090) bot t om view (pins up) 2.29 (0.090) 0.10 (0.004) max for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 23 . 8- lead standard small outline package , with exposed pa d [ soic_n_ep ] narrow body (rd-8-1) dimensions shown in millimeters and (inches) 071008- a compliant t o jedec s t andards mo-187-aa-t 0.70 0.55 0.40 8 0 0.94 0.86 0.78 sea ting plane 1.10 max 0.15 0.10 0.05 0.40 0.33 0.25 5.05 4.90 4.75 2.26 2.16 2.06 1.83 1.73 1.63 3.10 3.00 2.90 3.10 3.00 2.90 8 5 4 1 0.65 bsc 0.525 bsc pin 1 indic at or coplanarit y 0.10 0.23 0.18 0.13 top view bot t om view exposed p ad for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 24 . 8 - lead mini small outline package with exposed pad [ mini_so _ ep ] (rh -8- 1) dimensions shown in millimeters ordering guide model uvlo optio n temperature range package description package option ordering quantity branding ADP3624ardz 1 4.5 v ?40c to +85c 8- lead standard small outline package (soic_n_ep) rd -8-1 ADP3624ardz - rl 1 4.5 v ?40c to +85c 8- lead standard small outline package (soic_n_ep), tape reel rd -8-1 2,500 ADP3624arhz 1 4.5 v ?40c to +85c 8- lead mini small outline package (mini_so_ep) rh -8-1 p4 ADP3624arhz - rl 1 4.5 v ?40c to +85c 8- lead mini small outline package (mini_so_ep), tape reel rh -8-1 3,000 p4 adp3634ardz 1 9.5 v ?40c to +85c 8- lead standard small outline package (soic_n_ep) rd -8-1 adp3634ardz - rl 1 9.5 v 8- lead standard small outline package (soic_n_ep), tape reel rd -8-1 2,500 adp3634arhz 1 9.5 v 8- lead mini small outline package (mini_so_ep) rh -8-1 l4 adp3634arhz - rl 1 9.5 v 8- lead mini small outline package (mini_so_ep), tape reel rh -8-1 3,000 l4 1 z = rohs compliant part.
ADP3624/adp3634 rev. 0 | page 14 of 16 notes
ADP3624/adp3634 rev. 0 | page 15 of 16 notes
ADP3624/adp3634 rev. 0 | page 16 of 16 notes ? 2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective o wners. d08132 -0- 5/09(0)

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